In the technology of recent advanced high-speed semiconductor devices, use of the gate length of 0.1 μm or less is becoming possible with the progress in the art of ultrafine semiconductor fabrication processes. Generally, operational speed of a semiconductor device is improved with device miniaturization, while there is a need, in such extremely miniaturized semiconductor devices, to reduce the thickness of the gate insulation film thereof with the decrease of the gate length achieved as a result of the device miniaturization.
When the gate length has been reduced to 0.1 μm or less, on the other hand, the thickness of the gate insulation film has to be reduced to 1-2 nm or less when a conventional thermal oxide film is used for the gate insulation film. In such an extremely thin gate insulation film, however, there inevitably arises a problem of increased tunneling current, while such an increased tunneling current causes the problem of large gate leakage current.
In view of the situation noted above, there has been a proposal of using a high-dielectric material having a much larger specific dielectric constant as compared with a thermal oxide film and thus capable of achieving a small SiO2-equivalent thickness while maintaining a large physical thickness, for the gate insulation film. Such a high-K material includes Ta2O5, Al2O3, ZrO2, HfO2, ZrSiO4, HfSiO4, and the like. By using such a high-K dielectric material, it becomes possible to use the physical thickness of about 10 nm in ultra high-speed semiconductor devices having a gate length of 0.1 μm or less. Thereby, the gate leakage current caused by tunneling effect is successfully suppressed.
For example, a Ta2O5 film has been formed by a CVD process while using Ta(OC2H5)5 and O2 as gaseous sources. In a typical example, the CVD process is conducted under a reduced pressure at a temperature of about 480° C. or more. The Ta2O5 film thus formed is then subjected to a thermal annealing process in an oxidizing ambient and the oxygen defects in the film are compensated. Further, the film undergoes crystallization. The Ta2O5 film thus crystallized shows a large specific dielectric constant.
From the viewpoint of increasing carrier mobility in the channel region, it is preferable to provide an extremely thin base oxide film having a thickness of 1 nm or less, preferably 0.8 nm or less, between the high-K dielectric gate oxide film and the silicon substrate. This base oxide film has to be extremely thin. Otherwise, the effect of using the high-K dielectric film for the gate insulation film is cancelled out. On the other hand, such an extremely thin base oxide film is required also to cover the silicon substrate surface uniformly, without forming defects such as surface states.
Conventionally, rapid thermal oxidation (RTO) process of a silicon substrate (See, for example, Patent Document No. 1) has been used when forming a thin gate oxide film. When such an RTO process is used for forming a thermal oxide film with the desired thickness of 1 nm or less, there is a need of decreasing the processing temperature at the time of the film formation. However, such a thermal oxide film formed at low temperature tends to contain a large amount of surface states and is not suitable for the base oxide film of a high-K dielectric gate oxide film.
FIG. 1 shows the schematic construction of a high-speed semiconductor device 100 having a high-K dielectric gate insulation film.
Referring to FIG. 1, the semiconductor device 10 is constructed on a silicon substrate 11 and includes a high-K dielectric gate insulation film such as Ta2O5, Al2O3, ZrO2, HfO2, ZrSiO4, HfSiO4, and the like, formed on the silicon substrate 11 via a thin base oxide film 12. Further, a gate electrode 14 is formed on the high-K dielectric gate insulation film 13.
In the semiconductor device 10 of FIG. 1, there is conducted nitrogen (N) doping on the surface part of the base oxide film 12 within the extent that a flat interface is maintained between the silicon substrate 11 and the base oxide film 12. As a result of the nitrogen doping, the base oxide film 12 includes an oxynitride film 12A. In view of the large specific dielectric constant of such a silicon oxynitride film larger than that of a silicon oxide, it becomes possible to reduce the oxide-equivalent thickness of the base oxide film 12 further, by forming the oxynitride film 12A in the base oxide film 12.
As explained before, it is preferable that the base oxide film 12 has as small thickness as possible in such a high-speed semiconductor device 10.
However, it has been extremely difficult to form the base oxide film 12 with the thickness of 1 nm or less, such as 0.8 nm or less, or even approximately 0.4 nm corresponding to a thickness of 2-3 atomic layers, while simultaneously maintaining uniformity and reproducibility.
In order that the high-K dielectric gate insulation film 13 formed on the base oxide film 12 performs as a high-K dielectric film, it is necessary to crystallize the deposited high-K dielectric film 13 by a thermal annealing process and conduct compensation process of oxygen vacancy defects. However, such a thermal annealing process applied to the high-K dielectric gate insulation film 13 causes an increase of thickness in the base oxide film 12, and the desired decrease of the effective thickness of the gate insulation film, achieved by the use of the high-K dielectric gate insulation film 13, is more or less cancelled out.
Such an increase of thickness of the base oxide film 12 associated with the thermal annealing process suggests the possibility of mutual diffusion of oxygen atoms and silicon atoms and associated formation of a silicate transition layer, or the possibility of growth of the base oxide film 12 caused by the penetration of oxygen into the silicon substrate. Such a problem of increase of the base oxide film 12 with thermal annealing process becomes a particularly serious problem in the case the thickness of the base oxide film 12 is reduced to several atomic layers or less.    Patent Document No. 1: Japanese Laid-Open Patent Application No. 5-47687